PIC18F2610-E/SO【PDF 144/234 页】IC MCU FLASH 32KX16 28SOIC

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Sheet目录3878

140页 141页 142页 143页 [144页]145页 146页 147页 148页

PIC16F87XA

DS39582B-page 226

2003 Microchip Technology Inc.

Special Function Registers ................................................ 19

Special Function Registers (SFRs) .................................... 19

Speed, Operating ................................................................. 1

SPI Mode ..................................................................... 71, 77

Associated Registers ................................................. 79

Bus Mode Compatibility ............................................. 79

Effects of a Reset ....................................................... 79

Enabling SPI I/O ......................................................... 75

Master Mode .............................................................. 76

Master/Slave Connection ........................................... 75

Serial Clock ................................................................ 71

Serial Data In ............................................................. 71

Serial Data Out ........................................................... 71

Slave Select ............................................................... 71

Slave Select Synchronization ..................................... 77

Sleep Operation ......................................................... 79

SPI Clock ................................................................... 76

Typical Connection ..................................................... 75

SPI Mode Requirements .................................................. 190

SS ...................................................................................... 71

SSP

SPI Master/Slave Connection .................................... 75

SSPADD Register .............................................................. 20

SSPBUF Register .............................................................. 19

SSPCON Register .............................................................. 19

SSPCON2 Register ............................................................ 20

SSPIF ................................................................................. 26

SSPOV ............................................................................. 101

SSPSTAT Register ............................................................ 20

R/W Bit ................................................................. 84, 85

Stack .................................................................................. 30

Overflows ................................................................... 30

Underflow ................................................................... 30

Status Register

C Bit ........................................................................... 22

DC Bit ......................................................................... 22

IRP Bit ........................................................................ 22

PD Bit ................................................................. 22, 147

RP1:RP0 Bits ............................................................. 22

TO Bit ................................................................. 22, 147

Z Bit ............................................................................ 22

Synchronous Master Reception

Associated Registers ............................................... 123

Synchronous Master Transmission

Associated Registers ............................................... 122

Synchronous Serial Port Interrupt ...................................... 26

Synchronous Slave Reception

Associated Registers ............................................... 125

Synchronous Slave Transmission

Associated Registers ............................................... 125

T1CKPS0 Bit ...................................................................... 57

T1CKPS1 Bit ...................................................................... 57

T1CON Register ................................................................. 19

T1OSCEN Bit ..................................................................... 57

T1SYNC Bit ........................................................................ 57

T2CKPS0 Bit ...................................................................... 61

T2CKPS1 Bit ...................................................................... 61

T2CON Register ................................................................. 19

TAD ................................................................................... 131

Time-out Sequence .......................................................... 148

Timer0 ................................................................................ 53

Associated Registers ................................................. 55

Clock Source Edge Select (T0SE Bit) ....................... 23

Clock Source Select (T0CS Bit) ................................. 23

External Clock ............................................................ 54

Interrupt ..................................................................... 53

Overflow Enable (TMR0IE Bit) ................................... 24

Overflow Flag (TMR0IF Bit) ................................24, 154

Overflow Interrupt .................................................... 154

Prescaler .................................................................... 54

T0CKI ......................................................................... 54

Timer0 and Timer1 External Clock Requirements ........... 185

Timer1 ................................................................................ 57

Associated Registers ................................................. 60

Asynchronous Counter Mode .................................... 59

Reading and Writing to ...................................... 59

Counter Operation ..................................................... 58

Operation in Timer Mode ........................................... 58

Oscillator .................................................................... 59

Capacitor Selection ............................................ 59

Prescaler .................................................................... 60

Resetting of Timer1 Registers ................................... 60

Resetting Timer1 Using a CCP Trigger Output ......... 59

Synchronized Counter Mode ..................................... 58

TMR1H ...................................................................... 59

TMR1L ....................................................................... 59

Timer2 ................................................................................ 61

Associated Registers ................................................. 62

Output ........................................................................ 62

Postscaler .................................................................. 61

Prescaler .................................................................... 61

Prescaler and Postscaler ........................................... 62

Timing Diagrams

A/D Conversion ........................................................ 195

Acknowledge Sequence .......................................... 104

Asynchronous Master Transmission ........................ 116

Asynchronous Master Transmission

(Back to Back) ................................................. 116

Asynchronous Reception ......................................... 118

Asynchronous Reception with

Address Byte First ........................................... 120

Asynchronous Reception with

Address Detect ................................................ 120

Baud Rate Generator with Clock Arbitration .............. 98

BRG Reset Due to SDA Arbitration During

Start Condition ................................................. 107

Brown-out Reset ...................................................... 184

Bus Collision During a Repeated

Start Condition (Case 1) .................................. 108

Bus Collision During Repeated

Start Condition (Case 2) .................................. 108

Bus Collision During Start Condition

(SCL = 0) ......................................................... 107

Bus Collision During Start Condition

(SDA Only) ....................................................... 106

Bus Collision During Stop Condition

(Case 1) ........................................................... 109

Bus Collision During Stop Condition

(Case 2) ........................................................... 109

Bus Collision for Transmit and Acknowledge .......... 105

Capture/Compare/PWM (CCP1 and CCP2) ............ 186

CLKO and I/O .......................................................... 183

Clock Synchronization ............................................... 91

External Clock .......................................................... 182

First Start Bit .............................................................. 99

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